The present invention relates generally to integrated circuit processing and more particularly to a method of repairing broken metal interconnection lines using selective tungsten deposition.
In high density integrated circuits such as gate arrays, for example, in order to achieve the maximum gate usage, multi-level metalization is employed. Typically, a second and third level of metal is deposited over intervening dielectric layers and underlying metalization layers that are interconnected by way of via interconnects to underlying gates. Typical integrated circuits employ 1.5 micron technology and the metal line spacings in this technology are on the order of 2.0 microns.
When an inter-dielectric oxide layer is deposited over a patterned metal layer, the closeness of the metal line spacing creates a trough in the oxide layer. The subsequently formed patterned metal layer often has breaks in the metal lines in the areas of these troughs.
Surface planarization techniques have been employed to attempt to minimize the formation of troughs and other voids. However, these techniques require numerous additional steps and do not always result in usable circuits. Consequently, the metal step coverage over abrupt trench and via openings is a major yield inhibitor in fabricating integrated circuits.